1. Field of the Invention
The present invention relates to a CMOS image sensor, and more particularly, to a phototransistor of a CMOS image sensor suitable for decreasing the size of layout, and a method for fabricating the phototransistor.
2. Discussion of the Related Art
Generally, an image sensor is a semiconductor device for converting an optical image into an electric signal. The image sensor can be broadly categorized into a charge coupled device (CCD) and a complementary metal oxide semiconductor (CMOS) image sensor.
In case of the CCD, respective metal-oxide-silicon MOS capacitors are positioned adjacently, wherein electric charge carriers are stored in and transferred to the capacitors. Meanwhile, the CMOS image sensor adopts the CMOS technology of using a control circuit and a signal processing circuit as the circumferential circuit. The CMOS image sensor uses the switching method of sequentially detecting output signals by forming the predetermined number of MOS transistors in correspondence with the number of pixels.
The CCD has the high power consumption and the complicated mask process. Also, it is impossible to provide the signal processing circuit inside the CCD chip, whereby it cannot be formed in one chip. In order to overcome these problems, the sub-micron CMOS fabrication technology has been researched and developed.
In the CMOS image sensor, the photo-sensing means is generally formed of a photodiode. Recently, instead of the photodiode, a phototransistor is used for the photo-sensing means, to improve the photo-sensing degree.
FIG. 1 is a circuit diagram of showing a unit pixel in a 3-T CMOS image sensor according to the related art.
As shown in FIG. 1, a unit pixel of a 3-T CMOS image sensor according to the related art is comprised of a phototransistor PT, and three NMOS transistors Rx, Dx and Sx.
The phototransistor PT is formed as a PMOS transistor structure in which a gate is connected with a semiconductor substrate. Accordingly, when the light is incident on the phototransistor PT, electrons are accumulated on the semiconductor substrate, whereby a gate potential is lowered. Due to the lowered gate potential, holes are accumulated to the lower side of gate. In proportion to the amount of accumulated holes, more electrons are accumulated to the semiconductor substrate. Thus, the gate potential becomes lower. As a result, the phototransistor PT functions as the photo-sensing means having the great photo-photosensitivity according to the repetitive mechanism. That is, the phototransistor PT is very sensitive to the small amount of light.
Among the three NMOS transistors, the reset transistor Rx discharges the electrons stored in a floating sensing node FSN to detect the signal. The drive transistor Dx changes an output voltage of a unit pixel by changing a current of a source follower according to the change on the potential of the floating sensing node FSN. The select transistor Sx is provided for switching and addressing.
In addition, a DC gate is a load transistor, which has a gate having a constant voltage applied thereto. That is, since the constant voltage is applied to the gate of the transistor, a constant current flows through the DC gate. Also, ‘VDD’ is a drive power voltage, ‘GND’ is a ground voltage, and ‘Signal Out’ is an output voltage of a unit pixel.
Hereinafter, a phototransistor of a CMOS image sensor according to the related art will be described with reference to the accompanying drawings.
FIG. 2 is a layout of a phototransistor according to the related art. FIG. 3 is a cross sectional view along A—A′ of FIG. 2.
As shown in FIG. 2 and FIG. 3, an N-well 12 is formed in a p-type semiconductor substrate 1 1, and an STI layer 13 is formed in a device isolation area of the p-type semiconductor substrate 11, whereby the semiconductor substrate 11 is divided into an active area and the device isolation area.
After that, a gate line 14 is formed by forming a gate oxide layer 21 on the active area of the semiconductor substrate 11. Then, source and drain 15 and 16 are formed at both sides of the gate line 14 in the active area of the semiconductor substrate 11, wherein the source and drain 15 and 16 are formed in the p-type. Also, an ohmic contact layer 17 is formed in the active area of the semiconductor substrate 11, wherein the ohmic contact layer 17 is formed at the predetermined interval from the gate line 14.
Then, contacts 18 and 19 are respectively formed on the gate line 14 and the ohmic contact layer 17, wherein the contacts 18 and 19 pass through an insulating interlayer (not shown). Herein, the contacts 18 and 19 are connected with each other by an upper metal layer 20. That is, the gate line 14 is connected with the N-well 12 through the contact 18, the metal layer 20, the contact 19 and the ohmic contact layer 17.
If applying a reverse bias to the N-well 12, the N-well 12 becomes a depletion layer. When the light is incident on the depletion layer, electron-hole pairs are generated. In this state, the holes are discharged to the semiconductor substrate 11, and the electrons are accumulated to the depletion layer.
As the electrons are accumulated to the depletion layer, the potential of the ohmic contact layer 17 is lowered, whereby the potential of the gate line 14 connected with the ohmic contact layer 17 is also lowered. Accordingly, the holes are accumulated to the lower side of the gate line 14. In proportion to the amount of accumulated holes, more electrons are accumulated to the depletion layer.
Accordingly, the potential of the ohmic contact layer 17 is lowered, and the potential of the gate line 14 is also lowered. Thus, more holes are accumulated to the lower side of the gate line 14. In proportion to the amount of accumulated holes, more electrons are accumulated to the depletion layer.
According to the repetitive mechanism, the phototransistor is very sensitive to the small amount of light. That is, the phototransistor serves as the photo-sensing means of the great photo-sensitivity.
However, the related art phototransistor has the following disadvantages.
In the related art phototransistor, the gate line 14 is formed at the predetermined interval from the ohmic contact layer 17. Accordingly, it is necessary to provide the additional area for design of the ohmic contact layer 17. That is, the entire layout area increases, and the chip size also increases.